NTT DATA Automobiligence Research Center, Ltd.

ZIPC Product


ZIPC Family


The definitive CASE tool for state modeling,
still ranked first in terms of customer adoption rates


Recent embedded software development is becoming larger and more complicated at a rapid pace. Conventional development focuses on designing basic cases. Therefore, oversights and omissions are often seen in abnormal cases and exceptional cases. Also, designing with sentences or free formats tends to cause discrepancies from specifications because only code parts are modified for errors.

In addition, a lot of man-hours for development are wasted by considerable reworking when errors become obvious for the first time after the program was completed because dynamic verification cannot be done until implementation. Not only for the areas required to meet functional safety standards, but also for supporting larger and more complicated development, it is necessary to design with formal or semi-formal notation.


ZIPC V10 is applicable for any system or software developments involving state transition.

  • By comprehensively designing a combination of events and states with a state transition table, you can prevent oversights of abnormal or exceptional cases.
  • Because dynamic verification is available during the abstract design stage, you can find and solve problems at the modeling stage.
  • Because program codes can be generated automatically from models verified adequately for their behavior, the number of errors at the implementation stage drops sharply to improve the quality of software and productivity of development dramatically.
  • Because program codes are generated from models, discrepancy between specifications and codes does not occur.

ZIPC V10 is applicable for any system or software developments involving state transition.The quality and productivity are improved dramatically with its simulation function by which you can find errors at the early design stage of embedded development, and auto generation function of C code preventing discrepancy between state transition models and the source codes.

Features of ZIPC V10

Dedicated editor for state transition table

Extended Hierarchy State Transition Matrix(EHSTM) covers expressions required for designing behaviors of embedded software.Hierarchization realizes state modeling with high maintainability and reusability.In addition, it equips with editors to edit diagrams of state, sequence, timing and relationship among tasks.

Affluent simulation functions

From a higher abstract stage for Japanese description to the state transition table at a detailed design level including C code, simulation is available in all design phases.Affluent simulation functions such as execution log generation, parameter watch and breakpoint setting enable you to find errors before implementation.

Code generation

C codes related to state transition decided by events and states are generated automatically.This reduces coding man-hours.Also, because codes are generated from the state transition table behaving properly, from which errors have been removed through simulation, high quality C codes without human errors can be generated.

Operational Environment
OS Windows8.1(32 bit, 64 bit)
Windows10(32 bit,64 bit)
CPU Equivalent to 1GHz or more
Memory 2GB RAM or more
Disk Capacity 1GB or more



If you have any question, inquiries, or support regarding instllation or other, please feel free to contact us.